There is a current interest in CMOS active pixel imagers for use as low cost imaging devices. A pixel circuit of a CMOS active pixel sensor (APS) is described below with reference to FIG. 1. Active pixel sensors can have one or more active transistors within the pixel, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors. FIG. 1 illustrates a pixel 4T cell 10 in an image sensor 5, where “4T” designates the use of four transistors to operate the pixel 10 as is commonly understood in the art. A 4T pixel has a photodiode 12, a transfer transistor 11 a reset transistor 13, a source follower transistor 14, and a row select transistor 15. It should be understood that FIG. 1 shows the circuitry for the operation of a single pixel, and that in practical use there will be an M-by-N array of identical pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The photodiode 12 converts incident photons to electrons that are transferred to a storage node, such as a floating diffusion node FD, through transfer transistor 11. A source follower transistor 14 has its gate connected to node FD and amplifies the signal appearing at node FD. When a particular row containing pixel 10 is selected by the row select transistor 15, the signal amplified by transistor 14 is passed to a column line 17 to the readout circuitry. The photodiode 12 accumulates a photo-generated charge in a doped region of the substrate. It should be understood that the CMOS imager 5 might include a photogate or other photoconversion device, in lieu of a photodiode, for producing photo-generated charge.
A reset voltage source Vrst is selectively coupled through reset transistor 13 to node FD. The gate of transfer transistor 11 is coupled to a transfer control line which serves to control the transfer operation by which photodiode 12 is connected to node FD. The gate of reset transistor 13 is coupled to a reset control line, which serves to control the reset operation in which Vrst is connected to node FD. The row select control line is typically coupled to all of the pixels of the same row of the array. A supply voltage source is coupled to the source follower transistor 14. Column line 17 is coupled to all of the pixels of the same column of the array and typically has a current sink transistor 16 at one end. The gate of row select transistor 15 is coupled to row select control line.
As known in the art, for active pixel sensors of the type depicted in FIG. 1, a value may be read from pixel 5 using a two-step process. During a reset period, node FD is reset by turning on reset transistor 13, and the reset voltage is applied to node FD and read out to column line 17 by the source follower transistor 14 (through the activated row select transistor 15). During a charge integration period the photodiode 12 converts photons to electrons. After the integration period the transfer transistor 11 is then activated, allowing the electrons from photodiode 12 to collect at node FD. The charges at node FD are amplified by source follower transistor 14 and selectively passed to column line 17 by row access transistor 15. As a result, the two different values—the reset voltage (Vrst) and the image signal voltage (Vsig)—are readout from the pixel 10 and sent by the column line 17 to readout circuitry, where each voltage is sampled and held, subtracted (Vrst−Vsig), and converted into a digital value representing a pixel output.
All pixels in a row are read out simultaneously onto respective column lines 17 and stored in respective sample and hold circuits. Then the column circuitry in the sample and hold circuits are activated for reset and signal voltage readout processing.
FIG. 2 shows a CMOS active pixel sensor integrated circuit chip 2 that includes an array of pixels 5 and a controller 23 that provides timing and control signals to enable reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Arrays have dimensions of M-by-N pixels, with the size of the array 5 depending on a particular application. The array is read out a row at a time using a column parallel readout architecture. The controller 23 selects a particular row of pixels in the array 5 by controlling the operation of row addressing circuit 21 and row drivers 22 and selects columns for output by column addressing circuit 24. Charge signals stored in the selected row of pixels are provided on the column lines 17 (FIG. 1) to a readout circuit 25 in the manner described above. The pixel signals (reset voltage Vrst and image signal voltage Vsig) read from each of the columns can then be read out, sampled and held, subtracted by differential amplifier 26 and the result digitized by analog to digital converter 50. Pixel signals (Vrst, Vsig) corresponding to the readout reset signal (Vrst) and image signal (Vsig) are provided as respective inputs to the differential amplifier 26 for subtraction and subsequent processing. Alternatively, readout circuit 25 provides the two signals Vrst, Vsig to a differential analog-to-digital converter where the difference is converted to a digital value. The digitized difference signal is then sent to an image processor 80 which forms a digital image from the digital pixel array 5 signals and may also perform various image processing functions.
Some conventional analog to digital converters employ a sigma-delta architecture and employ pulse counters where the number of pulses counted at the end of a digital conversion period is the digital value representing the difference signal Vrst−Vsig, or a value correlated to that digital value. However, any one analog-to-digital conversion is not always completely accurate. For example, when an analog signal is being converted to a digital signal using sigma delta conversion, there can be a slight variation in the number of pulses that are provided representing a converted value. Thus, for an analog signal X provided to an ADC, one conversion can produce Y pulses. When at another time, that same analog signal X may convert as Y+2 pulses. At yet another time, analog signal X provided to an ADC may convert as Y−1 pulses. As such, each conversion may result in a slightly different digital representation of the analog signal X.
To increase the accuracy of the analog to digital conversion Y, sigma-delta converter which may be used in an imager to convert an analog signal to a digital signal multiple times, i.e., the output pulses are counted several times without resetting the counter. The pulse count then represents an average value over all of the multiple conversions and is then provided as the digital signal value to the image processor 80. The average of the pulse counts can be computed by continuously counting the total number of pulses for all of the multiple conversions and then dividing the total pulse count by the number of conversions, thus increasing the accuracy of the conversion.
Some conventional imagers are designed and manufactured with dual sets of readout circuits, one above of the pixel array and one below the pixel array, to help decrease the total amount of time required to read signals from the pixel array. FIG. 3 depicts a conventional imaging system 390 having a pixel array 340 having pairs of column lines of pixels with one column line of the pair being read out by an upper one of read out circuits, 350, 352, 354, 356, 358 and another column line of the pair being read out by a lower one of readout circuits, 360, 362, 364, 366, 368. Pixel array 340 is shown as set up in a Bayer pattern of red (“R”), blue (“B”), and two green (“G1”,“G2”) pixel cells though this is not the only color pattern which may be employed. In the imaging system 390, a pair of adjoining column lines 330, 331 of pixels e.g. pixels 370-379, and 380-389 have respective lower readout circuit, e.g., 360, and an upper readout circuit, e.g., 350. Typically, all of the green pixel cells (G1, G2) of the pixel array 340 are readout by the upper (or lower) set of read out circuits, 350, 352, 354, 356, 358, whereas the red and blue pixel cells are alternatively readout by the lower (or upper) set of readout circuits, 360, 362, 364, 366, 368.
The upper readout circuits and the lower readout circuits are operated to mutually read out signals from adjoining pixels in adjacent column lines 330, 331 e.g. 371, 381 in a same row at substantially the same time. For example, when row 391 is designated for readout, green G1 pixel 381 is readout by upper readout circuit 350 at substantially the same time that red pixel 371 is readout by lower readout circuit 360.
FIG. 4 is similar to FIG. 3, but depicts the readout from the pixel array 340 when the next row 392 is read out. When row 392 is readout, the upper and lower readout circuits 350, 360, exchange column lines 330, 331 so green G2 pixel 372 is readout by upper readout circuit 350, and at substantially the same time, blue pixel 382 is readout by lower readout circuit 360. This process of alternating by row the assignments of column lines 330, 331 to the readout circuits 350, 360 continues through the readout of all rows of the pixel array 346.
One of the tasks which may be performed by a readout circuit 350, 352, 354, 356, 360, 362, 364, 366, 368 is the analog to digital conversion of the difference of the Vrst and Vsig analog signals (Vrst and Vsig) readout from a pixel. The readout circuits 350-358 and 360-368 may, as noted, use sigma-delta analog to digital conversion. A non-exclusive, examples of sigma-delta analog-to-digital converters which may be used in readout circuits 350-358, 360, 368 are disclosed in U.S. application Ser. No. 11/106,465 and 11/417,021, the disclosures of which are incorporated herein by reference.
For an N-bit conversion accuracy, a sigma-delta converter employs 2N clock cycles. Thus, if the analog-to-digital conversion accuracy is 12 bits, then 212=4096 clock cycles are employed. During the conversion process the analog signal is repeatedly converted during the period of 4096 clock cycles to improve conversion accuracy so that at the end of the conversion period the N-bit analog-to-digital converter counter contains a count value which is the accumulation of the multiple A/D conversion and thus represents an average of the multiple conversions.
In many instances it is desirable to bin together pixel signals or scale pixel signals of an image. This is typically performed by the image processor 80 which receives the digital pixel signals for a captured image and performs the binning and/or scaling operations in a horizontal and/or vertical direction of an image. There are may other processing operations also performed by the image processor 80 and the additional binning and/or scaling operations may slow the speed of operation of an image processing pipeline implemented by the image processor 80. Accordingly, a method, apparatus and system which off loads at least some of the binning and/or scaling operations from the processing performed by image processor 80 would be desirable.